Mpilog - Macromodeling via Parametric Identification of LOgic Gates

Mpilog generates behavioral macromodels for the I/O ports of digital integrated circuits. Mpilog macromodels are mathematical relations approximating the port electrical behavior of devices, thus completely hiding the internal structure of devices and preserving the proprietary information of vendors. They are obtained from a set of port voltage and current responses carrying the information of port behavior that can be obtained either via direct measurements or via circuit simulation by driving the port with suitable stimuli. Mpilog allows the implementation of macromodels as SPICE-like subcircuits or as direct equation descriptions via metalanguages like VHDL-AMS. Furthermore, macromodels can be directly used in any EDA tool supporting the IBIS ver. 4.1 description of digital integrated circuits as externally defined models.

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